It is generally known that a continuing increase in carrier frequency for new RF applications is required. This is due to the need to realize higher data rates and to the fact that lower frequency bands are becoming more and more congested. The increase in frequency pushes the required cut-off frequency of RF technologies to increasingly higher values. Important Figure of merits (FOMs) in RF applications are the maximum frequencies for current gain fT, power gain fmax and voltage gain fA, respectively.
It goes without saying that the HBT is an improvement of the bipolar junction transistor (BJT) that handles signals of high frequencies up to several hundred GHz. The HBT is common in modern ultra-phase circuits, preferably in RF systems. A main difference between the HBT and the BJT is the use of different semiconductor materials for the emitter and base regions which thus creates a heterojunction.
The portion of integrated circuit fabrication (BiCMOS technology) where the active components, such as transistors or resistors, are interconnected with wiring on the wafer is called back-end-of-the-line (BEOL). BEOL generally begins when the first layer of metal is deposited on the wafer. It includes contacts, insulator, metal levels and bonding sites for chip-to-package connections.
Since the total epi stack (also called total epitaxial layer stack) of the HBT, i.e. collector and base, is grown in one go, the HBT is called GRINGO HBT. The HBT is usually grown on top of predefined active areas, resulting in a device protruding from the CMOS active area surface. Through this protrusion the chemical mechanical planarization (CMP) steps required for manufacturing the HBT does not affect the CMOS area, making this implementation well compatible with CMOS and therefore suitable as a true BiCMOS technology. The grown epi stack is typically patterned with a dummy emitter pedestal making the whole device structure self-aligned to the emitter. The base connection can be made by diffusion from a boron-doped poly-Si layer. This enables a low base resistance down to 100 Ωμm and a very steep lateral doping profile. The collector connection can be done by a “buried layer” type of implant but also with other, less highly doped, implants, such as the already present n-well implant. In CMOS technology a “twin tub” process is utilized to form a discrete, p-type well region (“p-well” in short) into which e.g. an NFET (n-doped field effect transistor) can be formed, and a discrete, n-type well region (“n-well” in short) into which e.g. a PFET (p-doped field effect transistor) can be formed.
An integration scheme of a GRINGO HBT is described in the following: After forming Shallow Trench Isolation (STI) regions and CMOS gate stack deposition the gate stack is patterned either already for defining the CMOS transistors or, preferably, to open up the areas for the HBTs. Subsequently, a seed layer is deposited and patterned. This seed layer typically is an oxide-nitride stack and also serves as a CMOS protection layer. Next, the HBT collector and base epi are grown. Then, the dummy emitter pedestal stack is deposited, consisting typically of oxide-nitride or oxide-nitride-oxide. The dummy emitter is patterned with a resist mask and the underlying silicon is etched down to the seed layer, removing it everywhere except underneath the dummy emitter. Then, a high density plasma (HDP) oxide is deposited, possibly preceded by a thin nitride liner. The HDP oxide is subsequently planarized with CMP. It is noted that dummy structures for CMP are usually required for obtaining reasonable thickness uniformity. Further, the HDP oxide is etched down by, for instance, an HF etch to a level below the intrinsic base. If the nitride liner is present it is etched subsequently. Then an in-situ boron-doped poly-Si layer is deposited and planarized with CMP down to or above the dummy emitter pedestal top level. A dry etch is then used to etch the poly-Si such that its top surface is touching the nitride of the dummy emitter pedestal, for instance half-way. The poly-Si is then oxidized, using for instance wet oxidation. Finally, the dummy emitter is removed, preferably using wet etch, and inside spacers are formed in the created emitter window. The emitter is defined by either epitaxial growth or poly-Si deposition. The emitter is subsequently patterned and the oxide on top of the base poly-Si is removed. The base poly-Si is then etched as well as the underlying HDP oxide, all selectively towards this CMOS protection layer. The seed layer is removed by a wet etch and conventional processing continuous, i.e. gate patterning, source/drain formation, silicidation and standard back-end processing.
An HDP oxide is a silicon oxide (SiO2) layer deposited using a Plasma Enhanced Chemical Vapor Deposition (PECVD) technique. An HDP oxide is capable of filling wide trenches without creating a void and is usually used in STI trench filling. Thus, an HDP oxide layer corresponds to an electrically insulating layer.
FIG. 1 illustrates the elementary processes involved in a Chemical Vapor Deposition (CVD) technique. In step A of FIG. 1 the transport of the precursor(s) with the carrier gas to the reaction chamber and to the wafer surface is depicted. In this step, convection and diffusion are the main processes involved. In step B adsorption or chemisorptions of the precursor(s) at the wafer surface occurs. Then, in step C chemical surface reaction including dissociation and surface diffusion occurs, followed by step D, during which film growth, desorption of volatile reaction products, transport of reaction products away from the wafer surface, i.e. diffusion, is involved. Finally, in step E the transport of reaction products with the carrier gas out of the reactor occurs. To sum up, the CVD process involves chemical reactions and, thus, an activation (i.e. an energy source) is required. In the PECVD technique, on the other hand, the required energy source is provided through a plasma. The advantages of PECVD are its high deposition rate and its low deposition temperature which typically is approx. 250° C. to 400° C.
In general, it is difficult to increase the maximum frequencies and, thus, the speed of the intrinsic device of a bipolar transistor. At the same time care has to be taken on reducing the impact of parasitic components attributed to the extrinsic parts of the semiconductor device. The extrinsic collector-base capacitance and the base resistance have a large impact in this respect. Reduction of these parasitic components is therefore the main driver behind the improvement in speed obtained in BiCMOS technologies.
In WO 2007/144828 A1a semiconductor device with a substrate and a semiconductor body comprising a bipolar transistor with in that order a collector region, a base region, and an emitter region is provided. The semiconductor body comprises a projecting mesa comprising at least a portion of the collector region and the base region, which mesa is surrounded by an isolation region. The semiconductor device also comprises a field effect transistor (FET) with a source region, a drain region, an interposed channel region, a superimposed gate dielectric, and a gate region, which gate region forms a highest part of the FET, and the height of the mesa is larger than the height of the gate region. Therefore, the bipolar transistor has been defined with an intrinsic part while the parasitic contributions of the extrinsic parts have been decreased.
In US 2005/0199907 A1 a structure and a method are described for making a bipolar transistor, wherein the bipolar transistor includes a collector, an intrinsic base overlying the collector, an emitter overlying the intrinsic base, and an extrinsic base spaced from the emitter by a gap. The gap includes at least one of an air gap and a vacuum void.